1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and a method of fabricating the same, and more particularly, to an align key for thin film transistor on a color filter (TOC)-type or color filter on thin film transistor (COT)-type LCD device and method of fabricating the same.
2. Discussion of the Related Art
As the information age rapidly evolves, a necessity for a flat panel display, which has advantages such as being thin, being lightweight, and having lower power consumption, has been increased. Liquid crystal display (LCD) devices are actively applied to notebook computers and desktop monitors, because of their superiority in resolution, display of color images and displaying quality. For example, active matrix liquid crystal display (AMLCD) devices, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are widely used because of their high resolution and superiority in displaying moving images.
In general, an LCD device is fabricated through an array substrate forming process, a color filter substrate forming process, and a liquid crystal cell forming process. A thin film transistor and a pixel electrode are formed in the array substrate forming process, and a color filter and a common electrode are formed in the color filter substrate forming process. Liquid crystal material is then injected between the array and color filter substrates in the liquid crystal cell forming process. The liquid crystal cell forming process commonly comprises an alignment layer forming process, a cell gap forming process, assembling process, a cell cutting process, and a liquid crystal injection process.
FIG. 1 is a cross-sectional view of a liquid crystal display (LCD) device according to the related art. In FIG. 1, an LCD device includes upper and lower substrates 10 and 30 spaced apart from each other with a predetermined space therebetween, and a liquid crystal material layer 50 disposed between the upper and lower substrates 10 and 30. A gate electrode 32 and a gate insulating layer 34 are sequentially formed on a transparent substrate 1 of the lower substrate 30. In addition, a semiconductor layer 36, which has an active layer 36a and an ohmic contact layer 36b, is formed over the gate electrode 32. Source and drain electrodes 38 and 40 are then formed spaced apart from each other on the semiconductor layer 36. A channel ch exposing a portion of the active layer 36a is formed between the source and drain electrodes 38 and 40. The gate electrode 32, the semiconductor layer 36, the channel ch, and the source and drain electrodes 38 and 40 form a thin film transistor T.
Furthermore, a gate line (not shown) is formed in a first direction connected to the gate electrode 32, and a data line (not shown) is formed in a second direction connected to the source electrode 38, such that the data line is perpendicular to the gate line. The data line defines a pixel region P by crossing the gate line. In addition, a passivation layer 42, which has a drain contact hole 44, is formed on the thin film transistor T. A pixel electrode 48, which contacts the drain electrode 40 through the drain contact hole 44, is formed in the pixel region P. A color filter 14, which filters light of a particular wavelength range, is formed beneath a transparent substrate 1 of the upper substrate 10.
Moreover, a black matrix 12 is formed in a boundary between each pixel region P to prevent a light leakage in the thin film transistor T region and an incoming of light into the thin film transistor T. A common electrode 16 is formed beneath the color filter 14 and the black matrix 12 to apply voltage to the liquid crystal layer 50. In addition, a seal pattern 52 is formed along edges of the first and second substrates 10 and 30 to prevent leakage of the liquid crystal between the first and second substrates 10 and 30. The seal pattern 52 is formed before the assembling process of the first and second substrates 10 and 30. Furthermore, the seal pattern 52 keeps a constant cell gap distance, thereby making the liquid crystal material injection process easier and preventing any injected liquid crystal material from leaking.
The LCD device further has alignment layers (not shown) between the upper substrate 10 and the liquid crystal layer 50, and between the lower substrate 30 and the liquid crystal layer 50. An aligning error margin for the assembling process of the first and second substrates 10 and 30 is commonly less than a few micrometers. However, if the upper and lower substrates 10 and 30 are aligned and attached with an aligning margin larger than the error margin of a few micrometers, display quality of the liquid crystal display deteriorates due to a light leakage during operation of the liquid crystal cell.
Furthermore, as the liquid crystal display (LCD) device becomes more and more integrated to display high quality images, space between elements becomes narrower. Accordingly, if there is a minor assembling error and thus an element is disposed in a position other than an initially designed position, a color reproduction quality is deteriorated.
Moreover, an LCD device, which has a structure wherein the color filter and the thin film transistor are formed in separate substrates, has the following disadvantages. First, assembling accuracy and aperture ratio may be decreased due to the misalignment of the array and color filter substrates. Second, if the assembling margin is reduced to increase the aperture ratio, light leakage phenomenon may occur. Third, because the color filter substrate and the array substrate should be formed in separate processes, it takes a long time to manufacture a liquid crystal panel. Thus, a TOC/COT-type LCD device has been suggested, wherein the thin film transistor and the color filter are formed in the same substrate.
FIG. 2 is a cross-sectional view of a TOC/COT-type LCD device according to the related art. In FIG. 2, a liquid crystal layer 90 is disposed between upper and lower substrates 60 and 70. A color filter 72 is formed on a transparent substrate 1 of the lower substrate 70. In addition, a flattening layer 74 is formed in each boundary for each color of the color filter 72 and on the color filter 72. An array element I is formed on the flattening layer 74, wherein the array element I has a thin film transistor T and a pixel electrode 78. Furthermore, a black matrix 62 is formed beneath the upper substrate 60 corresponding to the thin film transistor T to prevent light from flowing into the thin film transistor T. A common electrode 64 is formed beneath the black matrix 62. Because the array element I is disposed over the color filter 72, the color filter 72 can be divided into sections for each color. Light leakage can be prevented by the electro lines of the array element I that is formed of opaque material.
FIG. 3A is a plan view of an upper substrate for a TOC/COT-type LCD device according to the related art, and FIG. 3B is a magnified view of an area IIIA of FIG. 3A. In FIG. 3A, the upper substrate 60 has an active area IIA and a non-active area IIB. The common electrode 64 is extended to a boundary region of the active area IIA and the non-active area IIB. The black matrix 62 is formed in each pixel region of the active area IIA corresponding to the thin film transistor T (not shown) of the lower substrate (not shown). Align keys 94 are formed with same material as the black matrix in each corner of the non-active area IIB. A seal pattern 92 having an injection hole 91 is formed along edges of the common electrode 64 to assemble the upper and lower substrates 60 and 70 and form a cell gap. In FIG. 3B, the seal pattern 92 has a concave portion IIIB that exposes a portion of the common electrode 64. A silver dot 93, which is formed with silver (Ag) paste, is formed on the common electrode 64 corresponding to the concave portion IIIB of the seal pattern 92. The silver dot 93 serves to connect the upper and lower substrates 60 and 70 electrically and generally is formed by a point dotting method using a dispenser.
As stated above, the manufacturing process for the upper substrate 60 of the TOC/COT-type LCD device is complex because the process includes many processes, such as forming the common electrode 64, forming the black matrix 62 and the align key 94 with organic material or metal material, forming the seal pattern 92 and forming the silver dot 93. If the black matrix 62 is formed on the upper substrate 60, an assembling accuracy of the upper and lower substrates 60 and 70 may be decreased owing to an aligning margin with the thin film transistor T on the lower substrate 70. If the aligning margin is decreased, light leakage current may occur. Besides, because the black matrix 62 and the align key is formed by a photolithographic masking process that comprises a coating process, a light exposure process, a developing process, and an etching process, an accuracy of the align key 94, which is usually formed to have scores of micrometers (μm) pattern, is decreased and production yield may be low.